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<!DOCTYPE html> <!--[if IE 8]><html class="no-js lt-ie9" lang="en" > <![endif]--> <!--[if gt IE 8]><!--> <html class="no-js" lang="en" > <!--<![endif]--> <head> <meta charset="utf-8"> <meta name="viewport" content="width=device-width, initial-scale=1.0"> <title>Recommendations for KVM CPU model configuration on x86 hosts — QEMU qemu-kvm-6.2.0-53.module+el8.10.0+2055+8eb7870b.4 documentation</title> <link rel="shortcut icon" href="../../_static/qemu_32x32.png"/> <link rel="stylesheet" href="../../_static/css/theme.css" type="text/css" /> <link rel="stylesheet" href="../../_static/pygments.css" type="text/css" /> <link rel="index" title="Index" href="../../genindex.html" /> <link rel="search" title="Search" href="../../search.html" /> <link rel="next" title="Paravirtualized KVM features" href="kvm-pv.html" /> <link rel="prev" title="i440fx PC (pc-i440fx, pc)" href="pc.html" /> <script src="../../_static/js/modernizr.min.js"></script> </head> <body class="wy-body-for-nav"> <div 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Emulation Guest Hardware Specifications</a></li> <li class="toctree-l1"><a class="reference internal" href="../../devel/index.html">Developer Information</a></li> </ul> </div> </div> </nav> <section data-toggle="wy-nav-shift" class="wy-nav-content-wrap"> <nav class="wy-nav-top" aria-label="top navigation"> <i data-toggle="wy-nav-top" class="fa fa-bars"></i> <a href="../../index.html">QEMU</a> </nav> <div class="wy-nav-content"> <div class="rst-content"> <div role="navigation" aria-label="breadcrumbs navigation"> <ul class="wy-breadcrumbs"> <li><a href="../../index.html">Docs</a> »</li> <li><a href="../index.html">System Emulation</a> »</li> <li><a href="../targets.html">QEMU System Emulator Targets</a> »</li> <li><a href="../target-i386.html">x86 System emulator</a> »</li> <li>Recommendations for KVM CPU model configuration on x86 hosts</li> <li class="wy-breadcrumbs-aside"> <a href="https://gitlab.com/qemu-project/qemu/blob/master/docs/system/i386/cpu.rst" class="fa fa-gitlab"> Edit on GitLab</a> </li> </ul> <hr/> </div> <div role="main" class="document" itemscope="itemscope" itemtype="http://schema.org/Article"> <div itemprop="articleBody"> <div class="section" id="recommendations-for-kvm-cpu-model-configuration-on-x86-hosts"> <h1>Recommendations for KVM CPU model configuration on x86 hosts<a class="headerlink" href="#recommendations-for-kvm-cpu-model-configuration-on-x86-hosts" title="Permalink to this headline">¶</a></h1> <p>The information that follows provides recommendations for configuring CPU models on x86 hosts. The goals are to maximise performance, while protecting guest OS against various CPU hardware flaws, and optionally enabling live migration between hosts with heterogeneous CPU models.</p> <div class="section" id="two-ways-to-configure-cpu-models-with-qemu-kvm"> <h2>Two ways to configure CPU models with QEMU / KVM<a class="headerlink" href="#two-ways-to-configure-cpu-models-with-qemu-kvm" title="Permalink to this headline">¶</a></h2> <ol class="arabic"> <li><p class="first"><strong>Host passthrough</strong></p> <p>This passes the host CPU model features, model, stepping, exactly to the guest. Note that KVM may filter out some host CPU model features if they cannot be supported with virtualization. Live migration is unsafe when this mode is used as libvirt / QEMU cannot guarantee a stable CPU is exposed to the guest across hosts. This is the recommended CPU to use, provided live migration is not required.</p> </li> <li><p class="first"><strong>Named model</strong></p> <p>QEMU comes with a number of predefined named CPU models, that typically refer to specific generations of hardware released by Intel and AMD. These allow the guest VMs to have a degree of isolation from the host CPU, allowing greater flexibility in live migrating between hosts with differing hardware. @end table</p> </li> </ol> <p>In both cases, it is possible to optionally add or remove individual CPU features, to alter what is presented to the guest by default.</p> <p>Libvirt supports a third way to configure CPU models known as “Host model”. This uses the QEMU “Named model” feature, automatically picking a CPU model that is similar the host CPU, and then adding extra features to approximate the host model as closely as possible. This does not guarantee the CPU family, stepping, etc will precisely match the host CPU, as they would with “Host passthrough”, but gives much of the benefit of passthrough, while making live migration safe.</p> </div> <div class="section" id="abi-compatibility-levels-for-cpu-models"> <h2>ABI compatibility levels for CPU models<a class="headerlink" href="#abi-compatibility-levels-for-cpu-models" title="Permalink to this headline">¶</a></h2> <p>The x86_64 architecture has a number of <a class="reference external" href="https://gitlab.com/x86-psABIs/x86-64-ABI/">ABI compatibility levels</a> defined. Traditionally most operating systems and toolchains would only target the original baseline ABI. It is expected that in future OS and toolchains are likely to target newer ABIs. The table that follows illustrates which ABI compatibility levels can be satisfied by the QEMU CPU models. Note that the table only lists the long term stable CPU model versions (eg Haswell-v4). In addition to what is listed, there are also many CPU model aliases which resolve to a different CPU model version, depending on the machine type is in use.</p> <table border="1" class="colwidths-given docutils" id="id1"> <caption><span class="caption-text">x86-64 ABI compatibility levels</span><a class="headerlink" href="#id1" title="Permalink to this table">¶</a></caption> <colgroup> <col width="40%" /> <col width="15%" /> <col width="15%" /> <col width="15%" /> <col width="15%" /> </colgroup> <thead valign="bottom"> <tr class="row-odd"><th class="head">Model</th> <th class="head">baseline</th> <th class="head">v2</th> <th class="head">v3</th> <th class="head">v4</th> </tr> <tr class="row-even"><th class="head">486-v1</th> <th class="head"> </th> <th class="head"> </th> <th class="head"> </th> <th class="head"> </th> </tr> </thead> <tbody valign="top"> <tr class="row-odd"><td>Broadwell-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>Broadwell-v2</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-odd"><td>Broadwell-v3</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>Broadwell-v4</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-odd"><td>Cascadelake-Server-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-even"><td>Cascadelake-Server-v2</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-odd"><td>Cascadelake-Server-v3</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-even"><td>Cascadelake-Server-v4</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-odd"><td>Conroe-v1</td> <td>✅</td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>Cooperlake-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-odd"><td>Denverton-v1</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>Denverton-v2</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>Dhyana-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>EPYC-Milan-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-odd"><td>EPYC-Rome-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>EPYC-Rome-v2</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-odd"><td>EPYC-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>EPYC-v2</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-odd"><td>EPYC-v3</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>Haswell-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-odd"><td>Haswell-v2</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>Haswell-v3</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-odd"><td>Haswell-v4</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>Icelake-Client-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-odd"><td>Icelake-Client-v2</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>Icelake-Server-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-odd"><td>Icelake-Server-v2</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-even"><td>Icelake-Server-v3</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-odd"><td>Icelake-Server-v4</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-even"><td>IvyBridge-v1</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>IvyBridge-v2</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>KnightsMill-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-odd"><td>Nehalem-v1</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>Nehalem-v2</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>Opteron_G1-v1</td> <td>✅</td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>Opteron_G2-v1</td> <td>✅</td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>Opteron_G3-v1</td> <td>✅</td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>Opteron_G4-v1</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>Opteron_G5-v1</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>Penryn-v1</td> <td>✅</td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>SandyBridge-v1</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>SandyBridge-v2</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>Skylake-Client-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>Skylake-Client-v2</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-odd"><td>Skylake-Client-v3</td> <td>✅</td> <td>✅</td> <td>✅</td> <td> </td> </tr> <tr class="row-even"><td>Skylake-Server-v1</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-odd"><td>Skylake-Server-v2</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-even"><td>Skylake-Server-v3</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-odd"><td>Skylake-Server-v4</td> <td>✅</td> <td>✅</td> <td>✅</td> <td>✅</td> </tr> <tr class="row-even"><td>Snowridge-v1</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>Snowridge-v2</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>Westmere-v1</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>Westmere-v2</td> <td>✅</td> <td>✅</td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>athlon-v1</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>core2duo-v1</td> <td>✅</td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>coreduo-v1</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>kvm32-v1</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>kvm64-v1</td> <td>✅</td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>n270-v1</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>pentium-v1</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>pentium2-v1</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>pentium3-v1</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>phenom-v1</td> <td>✅</td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-even"><td>qemu32-v1</td> <td> </td> <td> </td> <td> </td> <td> </td> </tr> <tr class="row-odd"><td>qemu64-v1</td> <td>✅</td> <td> </td> <td> </td> <td> </td> </tr> </tbody> </table> </div> <div class="section" id="preferred-cpu-models-for-intel-x86-hosts"> <h2>Preferred CPU models for Intel x86 hosts<a class="headerlink" href="#preferred-cpu-models-for-intel-x86-hosts" title="Permalink to this headline">¶</a></h2> <p>The following CPU models are preferred for use on Intel hosts. Administrators / applications are recommended to use the CPU model that matches the generation of the host CPUs in use. In a deployment with a mixture of host CPU models between machines, if live migration compatibility is required, use the newest CPU model that is compatible across all desired hosts.</p> <dl class="docutils"> <dt><code class="docutils literal notranslate"><span class="pre">Cascadelake-Server</span></code>, <code class="docutils literal notranslate"><span class="pre">Cascadelake-Server-noTSX</span></code></dt> <dd>Intel Xeon Processor (Cascade Lake, 2019), with “stepping” levels 6 or 7 only. (The Cascade Lake Xeon processor with <em>stepping 5 is vulnerable to MDS variants</em>.)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Skylake-Server</span></code>, <code class="docutils literal notranslate"><span class="pre">Skylake-Server-IBRS</span></code>, <code class="docutils literal notranslate"><span class="pre">Skylake-Server-IBRS-noTSX</span></code></dt> <dd>Intel Xeon Processor (Skylake, 2016)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Skylake-Client</span></code>, <code class="docutils literal notranslate"><span class="pre">Skylake-Client-IBRS</span></code>, <code class="docutils literal notranslate"><span class="pre">Skylake-Client-noTSX-IBRS}</span></code></dt> <dd>Intel Core Processor (Skylake, 2015)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Broadwell</span></code>, <code class="docutils literal notranslate"><span class="pre">Broadwell-IBRS</span></code>, <code class="docutils literal notranslate"><span class="pre">Broadwell-noTSX</span></code>, <code class="docutils literal notranslate"><span class="pre">Broadwell-noTSX-IBRS</span></code></dt> <dd>Intel Core Processor (Broadwell, 2014)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Haswell</span></code>, <code class="docutils literal notranslate"><span class="pre">Haswell-IBRS</span></code>, <code class="docutils literal notranslate"><span class="pre">Haswell-noTSX</span></code>, <code class="docutils literal notranslate"><span class="pre">Haswell-noTSX-IBRS</span></code></dt> <dd>Intel Core Processor (Haswell, 2013)</dd> <dt><code class="docutils literal notranslate"><span class="pre">IvyBridge</span></code>, <code class="docutils literal notranslate"><span class="pre">IvyBridge-IBR</span></code></dt> <dd>Intel Xeon E3-12xx v2 (Ivy Bridge, 2012)</dd> <dt><code class="docutils literal notranslate"><span class="pre">SandyBridge</span></code>, <code class="docutils literal notranslate"><span class="pre">SandyBridge-IBRS</span></code></dt> <dd>Intel Xeon E312xx (Sandy Bridge, 2011)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Westmere</span></code>, <code class="docutils literal notranslate"><span class="pre">Westmere-IBRS</span></code></dt> <dd>Westmere E56xx/L56xx/X56xx (Nehalem-C, 2010)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Nehalem</span></code>, <code class="docutils literal notranslate"><span class="pre">Nehalem-IBRS</span></code></dt> <dd>Intel Core i7 9xx (Nehalem Class Core i7, 2008)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Penryn</span></code></dt> <dd>Intel Core 2 Duo P9xxx (Penryn Class Core 2, 2007)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Conroe</span></code></dt> <dd>Intel Celeron_4x0 (Conroe/Merom Class Core 2, 2006)</dd> </dl> </div> <div class="section" id="important-cpu-features-for-intel-x86-hosts"> <h2>Important CPU features for Intel x86 hosts<a class="headerlink" href="#important-cpu-features-for-intel-x86-hosts" title="Permalink to this headline">¶</a></h2> <p>The following are important CPU features that should be used on Intel x86 hosts, when available in the host CPU. Some of them require explicit configuration to enable, as they are not included by default in some, or all, of the named CPU models listed above. In general all of these features are included if using “Host passthrough” or “Host model”.</p> <dl class="docutils"> <dt><code class="docutils literal notranslate"><span class="pre">pcid</span></code></dt> <dd><p class="first">Recommended to mitigate the cost of the Meltdown (CVE-2017-5754) fix.</p> <p>Included by default in Haswell, Broadwell & Skylake Intel CPU models.</p> <p class="last">Should be explicitly turned on for Westmere, SandyBridge, and IvyBridge Intel CPU models. Note that some desktop/mobile Westmere CPUs cannot support this feature.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">spec-ctrl</span></code></dt> <dd><p class="first">Required to enable the Spectre v2 (CVE-2017-5715) fix.</p> <p>Included by default in Intel CPU models with -IBRS suffix.</p> <p>Must be explicitly turned on for Intel CPU models without -IBRS suffix.</p> <p class="last">Requires the host CPU microcode to support this feature before it can be used for guest CPUs.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">stibp</span></code></dt> <dd><p class="first">Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some operating systems.</p> <p>Must be explicitly turned on for all Intel CPU models.</p> <p class="last">Requires the host CPU microcode to support this feature before it can be used for guest CPUs.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">ssbd</span></code></dt> <dd><p class="first">Required to enable the CVE-2018-3639 fix.</p> <p>Not included by default in any Intel CPU model.</p> <p>Must be explicitly turned on for all Intel CPU models.</p> <p class="last">Requires the host CPU microcode to support this feature before it can be used for guest CPUs.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">pdpe1gb</span></code></dt> <dd><p class="first">Recommended to allow guest OS to use 1GB size pages.</p> <p>Not included by default in any Intel CPU model.</p> <p>Should be explicitly turned on for all Intel CPU models.</p> <p class="last">Note that not all CPU hardware will support this feature.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">md-clear</span></code></dt> <dd><p class="first">Required to confirm the MDS (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091) fixes.</p> <p>Not included by default in any Intel CPU model.</p> <p>Must be explicitly turned on for all Intel CPU models.</p> <p class="last">Requires the host CPU microcode to support this feature before it can be used for guest CPUs.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">mds-no</span></code></dt> <dd><p class="first">Recommended to inform the guest OS that the host is <em>not</em> vulnerable to any of the MDS variants ([MFBDS] CVE-2018-12130, [MLPDS] CVE-2018-12127, [MSBDS] CVE-2018-12126).</p> <p>This is an MSR (Model-Specific Register) feature rather than a CPUID feature, so it will not appear in the Linux <code class="docutils literal notranslate"><span class="pre">/proc/cpuinfo</span></code> in the host or guest. Instead, the host kernel uses it to populate the MDS vulnerability file in <code class="docutils literal notranslate"><span class="pre">sysfs</span></code>.</p> <p class="last">So it should only be enabled for VMs if the host reports @code{Not affected} in the <code class="docutils literal notranslate"><span class="pre">/sys/devices/system/cpu/vulnerabilities/mds</span></code> file.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">taa-no</span></code></dt> <dd><p class="first">Recommended to inform that the guest that the host is <code class="docutils literal notranslate"><span class="pre">not</span></code> vulnerable to CVE-2019-11135, TSX Asynchronous Abort (TAA).</p> <p>This too is an MSR feature, so it does not show up in the Linux <code class="docutils literal notranslate"><span class="pre">/proc/cpuinfo</span></code> in the host or guest.</p> <p class="last">It should only be enabled for VMs if the host reports <code class="docutils literal notranslate"><span class="pre">Not</span> <span class="pre">affected</span></code> in the <code class="docutils literal notranslate"><span class="pre">/sys/devices/system/cpu/vulnerabilities/tsx_async_abort</span></code> file.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">tsx-ctrl</span></code></dt> <dd><p class="first">Recommended to inform the guest that it can disable the Intel TSX (Transactional Synchronization Extensions) feature; or, if the processor is vulnerable, use the Intel VERW instruction (a processor-level instruction that performs checks on memory access) as a mitigation for the TAA vulnerability. (For details, refer to Intel’s <a class="reference external" href="https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling">deep dive into MDS</a>.)</p> <p>Expose this to the guest OS if and only if: (a) the host has TSX enabled; <em>and</em> (b) the guest has <code class="docutils literal notranslate"><span class="pre">rtm</span></code> CPU flag enabled.</p> <p>By disabling TSX, KVM-based guests can avoid paying the price of mitigating TSX-based attacks.</p> <p>Note that <code class="docutils literal notranslate"><span class="pre">tsx-ctrl</span></code> too is an MSR feature, so it does not show up in the Linux <code class="docutils literal notranslate"><span class="pre">/proc/cpuinfo</span></code> in the host or guest.</p> <p class="last">To validate that Intel TSX is indeed disabled for the guest, there are two ways: (a) check for the <em>absence</em> of <code class="docutils literal notranslate"><span class="pre">rtm</span></code> in the guest’s <code class="docutils literal notranslate"><span class="pre">/proc/cpuinfo</span></code>; or (b) the <code class="docutils literal notranslate"><span class="pre">/sys/devices/system/cpu/vulnerabilities/tsx_async_abort</span></code> file in the guest should report <code class="docutils literal notranslate"><span class="pre">Mitigation:</span> <span class="pre">TSX</span> <span class="pre">disabled</span></code>.</p> </dd> </dl> </div> <div class="section" id="preferred-cpu-models-for-amd-x86-hosts"> <h2>Preferred CPU models for AMD x86 hosts<a class="headerlink" href="#preferred-cpu-models-for-amd-x86-hosts" title="Permalink to this headline">¶</a></h2> <p>The following CPU models are preferred for use on AMD hosts. Administrators / applications are recommended to use the CPU model that matches the generation of the host CPUs in use. In a deployment with a mixture of host CPU models between machines, if live migration compatibility is required, use the newest CPU model that is compatible across all desired hosts.</p> <dl class="docutils"> <dt><code class="docutils literal notranslate"><span class="pre">EPYC</span></code>, <code class="docutils literal notranslate"><span class="pre">EPYC-IBPB</span></code></dt> <dd>AMD EPYC Processor (2017)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Opteron_G5</span></code></dt> <dd>AMD Opteron 63xx class CPU (2012)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Opteron_G4</span></code></dt> <dd>AMD Opteron 62xx class CPU (2011)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Opteron_G3</span></code></dt> <dd>AMD Opteron 23xx (Gen 3 Class Opteron, 2009)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Opteron_G2</span></code></dt> <dd>AMD Opteron 22xx (Gen 2 Class Opteron, 2006)</dd> <dt><code class="docutils literal notranslate"><span class="pre">Opteron_G1</span></code></dt> <dd>AMD Opteron 240 (Gen 1 Class Opteron, 2004)</dd> </dl> </div> <div class="section" id="important-cpu-features-for-amd-x86-hosts"> <h2>Important CPU features for AMD x86 hosts<a class="headerlink" href="#important-cpu-features-for-amd-x86-hosts" title="Permalink to this headline">¶</a></h2> <p>The following are important CPU features that should be used on AMD x86 hosts, when available in the host CPU. Some of them require explicit configuration to enable, as they are not included by default in some, or all, of the named CPU models listed above. In general all of these features are included if using “Host passthrough” or “Host model”.</p> <dl class="docutils"> <dt><code class="docutils literal notranslate"><span class="pre">ibpb</span></code></dt> <dd><p class="first">Required to enable the Spectre v2 (CVE-2017-5715) fix.</p> <p>Included by default in AMD CPU models with -IBPB suffix.</p> <p>Must be explicitly turned on for AMD CPU models without -IBPB suffix.</p> <p class="last">Requires the host CPU microcode to support this feature before it can be used for guest CPUs.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">stibp</span></code></dt> <dd><p class="first">Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some operating systems.</p> <p>Must be explicitly turned on for all AMD CPU models.</p> <p class="last">Requires the host CPU microcode to support this feature before it can be used for guest CPUs.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">virt-ssbd</span></code></dt> <dd><p class="first">Required to enable the CVE-2018-3639 fix</p> <p>Not included by default in any AMD CPU model.</p> <p>Must be explicitly turned on for all AMD CPU models.</p> <p>This should be provided to guests, even if amd-ssbd is also provided, for maximum guest compatibility.</p> <p class="last">Note for some QEMU / libvirt versions, this must be force enabled when when using “Host model”, because this is a virtual feature that doesn’t exist in the physical host CPUs.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">amd-ssbd</span></code></dt> <dd><p class="first">Required to enable the CVE-2018-3639 fix</p> <p>Not included by default in any AMD CPU model.</p> <p>Must be explicitly turned on for all AMD CPU models.</p> <p class="last">This provides higher performance than <code class="docutils literal notranslate"><span class="pre">virt-ssbd</span></code> so should be exposed to guests whenever available in the host. <code class="docutils literal notranslate"><span class="pre">virt-ssbd</span></code> should none the less also be exposed for maximum guest compatibility as some kernels only know about <code class="docutils literal notranslate"><span class="pre">virt-ssbd</span></code>.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">amd-no-ssb</span></code></dt> <dd><p class="first">Recommended to indicate the host is not vulnerable CVE-2018-3639</p> <p>Not included by default in any AMD CPU model.</p> <p class="last">Future hardware generations of CPU will not be vulnerable to CVE-2018-3639, and thus the guest should be told not to enable its mitigations, by exposing amd-no-ssb. This is mutually exclusive with virt-ssbd and amd-ssbd.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">pdpe1gb</span></code></dt> <dd><p class="first">Recommended to allow guest OS to use 1GB size pages</p> <p>Not included by default in any AMD CPU model.</p> <p>Should be explicitly turned on for all AMD CPU models.</p> <p class="last">Note that not all CPU hardware will support this feature.</p> </dd> </dl> </div> <div class="section" id="default-x86-cpu-models"> <h2>Default x86 CPU models<a class="headerlink" href="#default-x86-cpu-models" title="Permalink to this headline">¶</a></h2> <p>The default QEMU CPU models are designed such that they can run on all hosts. If an application does not wish to do perform any host compatibility checks before launching guests, the default is guaranteed to work.</p> <p>The default CPU models will, however, leave the guest OS vulnerable to various CPU hardware flaws, so their use is strongly discouraged. Applications should follow the earlier guidance to setup a better CPU configuration, with host passthrough recommended if live migration is not needed.</p> <dl class="docutils"> <dt><code class="docutils literal notranslate"><span class="pre">qemu32</span></code>, <code class="docutils literal notranslate"><span class="pre">qemu64</span></code></dt> <dd>QEMU Virtual CPU version 2.5+ (32 & 64 bit variants)</dd> </dl> <p><code class="docutils literal notranslate"><span class="pre">qemu64</span></code> is used for x86_64 guests and <code class="docutils literal notranslate"><span class="pre">qemu32</span></code> is used for i686 guests, when no <code class="docutils literal notranslate"><span class="pre">-cpu</span></code> argument is given to QEMU, or no <code class="docutils literal notranslate"><span class="pre"><cpu></span></code> is provided in libvirt XML.</p> </div> <div class="section" id="other-non-recommended-x86-cpus"> <h2>Other non-recommended x86 CPUs<a class="headerlink" href="#other-non-recommended-x86-cpus" title="Permalink to this headline">¶</a></h2> <p>The following CPUs models are compatible with most AMD and Intel x86 hosts, but their usage is discouraged, as they expose a very limited featureset, which prevents guests having optimal performance.</p> <dl class="docutils"> <dt><code class="docutils literal notranslate"><span class="pre">kvm32</span></code>, <code class="docutils literal notranslate"><span class="pre">kvm64</span></code></dt> <dd><p class="first">Common KVM processor (32 & 64 bit variants).</p> <p class="last">Legacy models just for historical compatibility with ancient QEMU versions.</p> </dd> <dt><code class="docutils literal notranslate"><span class="pre">486</span></code>, <code class="docutils literal notranslate"><span class="pre">athlon</span></code>, <code class="docutils literal notranslate"><span class="pre">phenom</span></code>, <code class="docutils literal notranslate"><span class="pre">coreduo</span></code>, <code class="docutils literal notranslate"><span class="pre">core2duo</span></code>, <code class="docutils literal notranslate"><span class="pre">n270</span></code>, <code class="docutils literal notranslate"><span class="pre">pentium</span></code>, <code class="docutils literal notranslate"><span class="pre">pentium2</span></code>, <code class="docutils literal notranslate"><span class="pre">pentium3</span></code></dt> <dd>Various very old x86 CPU models, mostly predating the introduction of hardware assisted virtualization, that should thus not be required for running virtual machines.</dd> </dl> </div> </div> <div class="section" id="syntax-for-configuring-cpu-models"> <h1>Syntax for configuring CPU models<a class="headerlink" href="#syntax-for-configuring-cpu-models" title="Permalink to this headline">¶</a></h1> <p>The examples below illustrate the approach to configuring the various CPU models / features in QEMU and libvirt.</p> <div class="section" id="qemu-command-line"> <h2>QEMU command line<a class="headerlink" href="#qemu-command-line" title="Permalink to this headline">¶</a></h2> <p>Host passthrough:</p> <pre class="literal-block"> qemu-kvm -cpu host </pre> <p>Host passthrough with feature customization:</p> <pre class="literal-block"> qemu-kvm -cpu host,vmx=off,... </pre> <p>Named CPU models:</p> <pre class="literal-block"> qemu-kvm -cpu Westmere </pre> <p>Named CPU models with feature customization:</p> <pre class="literal-block"> qemu-kvm -cpu Westmere,pcid=on,... </pre> </div> <div class="section" id="libvirt-guest-xml"> <h2>Libvirt guest XML<a class="headerlink" href="#libvirt-guest-xml" title="Permalink to this headline">¶</a></h2> <p>Host passthrough:</p> <div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'host-passthrough'</span><span class="o">/></span> </pre></div> </div> <p>Host passthrough with feature customization:</p> <div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'host-passthrough'</span><span class="o">></span> <span class="o"><</span><span class="n">feature</span> <span class="n">name</span><span class="o">=</span><span class="s2">"vmx"</span> <span class="n">policy</span><span class="o">=</span><span class="s2">"disable"</span><span class="o">/></span> <span class="o">...</span> <span class="o"></</span><span class="n">cpu</span><span class="o">></span> </pre></div> </div> <p>Host model:</p> <div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'host-model'</span><span class="o">/></span> </pre></div> </div> <p>Host model with feature customization:</p> <div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'host-model'</span><span class="o">></span> <span class="o"><</span><span class="n">feature</span> <span class="n">name</span><span class="o">=</span><span class="s2">"vmx"</span> <span class="n">policy</span><span class="o">=</span><span class="s2">"disable"</span><span class="o">/></span> <span class="o">...</span> <span class="o"></</span><span class="n">cpu</span><span class="o">></span> </pre></div> </div> <p>Named model:</p> <div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'custom'</span><span class="o">></span> <span class="o"><</span><span class="n">model</span> <span class="n">name</span><span class="o">=</span><span class="s2">"Westmere"</span><span class="o">/></span> <span class="o"></</span><span class="n">cpu</span><span class="o">></span> </pre></div> </div> <p>Named model with feature customization:</p> <div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'custom'</span><span class="o">></span> <span class="o"><</span><span class="n">model</span> <span class="n">name</span><span class="o">=</span><span class="s2">"Westmere"</span><span class="o">/></span> <span class="o"><</span><span class="n">feature</span> <span class="n">name</span><span class="o">=</span><span class="s2">"pcid"</span> <span class="n">policy</span><span class="o">=</span><span class="s2">"require"</span><span class="o">/></span> <span class="o">...</span> <span class="o"></</span><span class="n">cpu</span><span class="o">></span> </pre></div> </div> </div> </div> </div> </div> <footer> <div class="rst-footer-buttons" role="navigation" aria-label="footer navigation"> <a href="kvm-pv.html" class="btn btn-neutral float-right" title="Paravirtualized KVM features" accesskey="n" rel="next">Next <span class="fa fa-arrow-circle-right"></span></a> <a href="pc.html" class="btn btn-neutral" title="i440fx PC (pc-i440fx, pc)" accesskey="p" rel="prev"><span class="fa fa-arrow-circle-left"></span> Previous</a> </div> <hr/> <div role="contentinfo"> <p> © Copyright 2021, The QEMU Project Developers. </p> </div> Built with <a href="http://sphinx-doc.org/">Sphinx</a> using a <a href="https://github.com/rtfd/sphinx_rtd_theme">theme</a> provided by <a href="https://readthedocs.org">Read the Docs</a>. <!-- Empty para to force a blank line after "Built with Sphinx ..." --> <p></p> <p>This documentation is for QEMU version 6.2.0.</p> <p><a href="../../about/license.html">QEMU and this manual are released under the GNU General Public License, version 2.</a></p> </footer> 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