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  <div class="section" id="a-profile-cpu-architecture-support">
<h1>A-profile CPU architecture support<a class="headerlink" href="#a-profile-cpu-architecture-support" title="Permalink to this headline">¶</a></h1>
<p>QEMU’s TCG emulation includes support for the Armv5, Armv6, Armv7 and
Armv8 versions of the A-profile architecture. It also has support for
the following architecture extensions:</p>
<ul class="simple">
<li>FEAT_AA32BF16 (AArch32 BFloat16 instructions)</li>
<li>FEAT_AA32HPD (AArch32 hierarchical permission disables)</li>
<li>FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)</li>
<li>FEAT_AES (AESD and AESE instructions)</li>
<li>FEAT_BF16 (AArch64 BFloat16 instructions)</li>
<li>FEAT_BTI (Branch Target Identification)</li>
<li>FEAT_DIT (Data Independent Timing instructions)</li>
<li>FEAT_DPB (DC CVAP instruction)</li>
<li>FEAT_DotProd (Advanced SIMD dot product instructions)</li>
<li>FEAT_FCMA (Floating-point complex number instructions)</li>
<li>FEAT_FHM (Floating-point half-precision multiplication instructions)</li>
<li>FEAT_FP16 (Half-precision floating-point data processing)</li>
<li>FEAT_FRINTTS (Floating-point to integer instructions)</li>
<li>FEAT_FlagM (Flag manipulation instructions v2)</li>
<li>FEAT_FlagM2 (Enhancements to flag manipulation instructions)</li>
<li>FEAT_HPDS (Hierarchical permission disables)</li>
<li>FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)</li>
<li>FEAT_JSCVT (JavaScript conversion instructions)</li>
<li>FEAT_LOR (Limited ordering regions)</li>
<li>FEAT_LRCPC (Load-acquire RCpc instructions)</li>
<li>FEAT_LRCPC2 (Load-acquire RCpc instructions v2)</li>
<li>FEAT_LSE (Large System Extensions)</li>
<li>FEAT_MTE (Memory Tagging Extension)</li>
<li>FEAT_MTE2 (Memory Tagging Extension)</li>
<li>FEAT_MTE3 (MTE Asymmetric Fault Handling)</li>
<li>FEAT_PAN (Privileged access never)</li>
<li>FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)</li>
<li>FEAT_PAuth (Pointer authentication)</li>
<li>FEAT_PMULL (PMULL, PMULL2 instructions)</li>
<li>FEAT_PMUv3p1 (PMU Extensions v3.1)</li>
<li>FEAT_PMUv3p4 (PMU Extensions v3.4)</li>
<li>FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)</li>
<li>FEAT_RNG (Random number generator)</li>
<li>FEAT_SB (Speculation Barrier)</li>
<li>FEAT_SEL2 (Secure EL2)</li>
<li>FEAT_SHA1 (SHA1 instructions)</li>
<li>FEAT_SHA256 (SHA256 instructions)</li>
<li>FEAT_SHA3 (Advanced SIMD SHA3 instructions)</li>
<li>FEAT_SHA512 (Advanced SIMD SHA512 instructions)</li>
<li>FEAT_SM3 (Advanced SIMD SM3 instructions)</li>
<li>FEAT_SM4 (Advanced SIMD SM4 instructions)</li>
<li>FEAT_SPECRES (Speculation restriction instructions)</li>
<li>FEAT_SSBS (Speculative Store Bypass Safe)</li>
<li>FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)</li>
<li>FEAT_TLBIRANGE (TLB invalidate range instructions)</li>
<li>FEAT_TTCNP (Translation table Common not private translations)</li>
<li>FEAT_TTST (Small translation tables)</li>
<li>FEAT_UAO (Unprivileged Access Override control)</li>
<li>FEAT_VHE (Virtualization Host Extensions)</li>
<li>FEAT_VMID16 (16-bit VMID)</li>
<li>FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)</li>
<li>SVE (The Scalable Vector Extension)</li>
<li>SVE2 (The Scalable Vector Extension v2)</li>
</ul>
<p>For information on the specifics of these extensions, please refer
to the <a class="reference external" href="https://developer.arm.com/documentation/ddi0487/latest">Armv8-A Arm Architecture Reference Manual</a>.</p>
<p>When a specific named CPU is being emulated, only those features which
are present in hardware for that CPU are emulated. (If a feature is
not in the list above then it is not supported, even if the real
hardware should have it.) The <code class="docutils literal notranslate"><span class="pre">max</span></code> CPU enables all features.</p>
</div>
<div class="section" id="r-profile-cpu-architecture-support">
<h1>R-profile CPU architecture support<a class="headerlink" href="#r-profile-cpu-architecture-support" title="Permalink to this headline">¶</a></h1>
<p>QEMU’s TCG emulation support for R-profile CPUs is currently limited.
We emulate only the Cortex-R5 and Cortex-R5F CPUs.</p>
</div>
<div class="section" id="m-profile-cpu-architecture-support">
<h1>M-profile CPU architecture support<a class="headerlink" href="#m-profile-cpu-architecture-support" title="Permalink to this headline">¶</a></h1>
<p>QEMU’s TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and
Armv8.1-M versions of the M-profile architucture.  It also has support
for the following architecture extensions:</p>
<ul class="simple">
<li>FP (Floating-point Extension)</li>
<li>FPCXT (FPCXT access instructions)</li>
<li>HP (Half-precision floating-point instructions)</li>
<li>LOB (Low Overhead loops and Branch future)</li>
<li>M (Main Extension)</li>
<li>MPU (Memory Protection Unit Extension)</li>
<li>PXN (Privileged Execute Never)</li>
<li>RAS (Reliability, Serviceability and Availability): “minimum RAS Extension” only</li>
<li>S (Security Extension)</li>
<li>ST (System Timer Extension)</li>
</ul>
<p>For information on the specifics of these extensions, please refer
to the <a class="reference external" href="https://developer.arm.com/documentation/ddi0553/latest">Armv8-M Arm Architecture Reference Manual</a>.</p>
<p>When a specific named CPU is being emulated, only those features which
are present in hardware for that CPU are emulated. (If a feature is
not in the list above then it is not supported, even if the real
hardware should have it.) There is no equivalent of the <code class="docutils literal notranslate"><span class="pre">max</span></code> CPU for
M-profile.</p>
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